The invention relates generally to methods for monitoring and controlling processes used in fabricating integrated circuit devices. More specifically, the invention relates to a method for detecting an endpoint during plasma etching of a film stack, such as a dielectric film stack.
In the fabrication of integrated circuits, features may be etched into film stacks and filled with different materials to form the desired circuitry. To facilitate ease of understanding, the disclosure herein will focus on dual damascene integration as one exemplary technique involving the etching of a film stack. It should be understood, however, that the techniques disclosed herein are not limited only to dual damascene integration and may apply to the etching of any film stack wherein an endpoint is required.
Generally speaking, dual damascene integration is used to form high-speed wiring interconnects in complex integrated circuit devices. In dual damascene integration, trenches and vias are formed in a low-permittivity (low-κ) material, such as a fluorosilicate glass (FSG), an organosilicate glass (OSG), e.g., BLACK DIAMOND or CORAL, or a spin-on organic (SOO), e.g., SILK or FLARE, and filled with copper or another suitable conductor. The copper is used to reduce the resistance of the metal interconnect lines, and the low-κ material is used to reduce parasitic capacitance between the metal interconnects.
FIG. 1A shows a dual damascene stack 100 formed on a copper line 102. In general, a dual-damascene stack is made of a sequence of hard masks and interlayer dielectrics. In the discussions that follow, terms such as “above” and “below,” which may be employed herein to discuss the spatial relationship among the layers, may, but need not always, denote a direct contact between the layers involved. It should be noted that other additional layers above, below, or between the layers shown or discussed may be present. Further, not all of the shown or discussed layers need necessarily be present and some or all may be substituted by other different layers.
For example, the dual damascene stack 100 includes a top hard mask 104, a dielectric film stack 106, and a diffusion barrier 108. The dielectric film stack 106 includes low-κ interlayer dielectrics 110, 112 and an embedded hard mask 114. The top hard mask 104 protects the interlayer dielectric 110 from chemicals used in photoresist stripping processes and may be omitted depending on the target application. The diffusion barrier 108 prevents undesirable diffusion of atoms between the copper 102 and the interlayer dielectric 112. The embedded hard mask 114 and diffusion barrier 108 act as etch stop layers for the trench and via etches, respectively.
There are two main approaches to dual-damascene integration: a trench-first approach and a via-first approach. In the trench-first approach, a via is patterned and etched in the dual-damascene stack 100 after a trench is formed in the stack 100. In the via-first approach, a trench is patterned and etched in the dual-damascene stack 100 after a via is formed in the stack 100. A less common approach to dual-damascene integration, called buried-via or self-aligned damascene process, involves patterning the embedded hard mask 114 prior to depositing the interlayer dielectric 110 and top hard mask 104 and etching the trench and via in the stack 100 in one step.
FIGS. 1B-1D illustrate an exemplary trench-first dual-damascene process. In FIG. 1B, a photoresist mask 116 having a trench pattern is applied on the top hard mask 104. A trench 118 is formed in the stack 100 by etching the trench mask 116 through the top hard mask 104 and through the interlayer dielectric 110, stopping on the embedded hard mask 114. In FIG. 1C, the trench mask (116 in FIG. 1B) has been stripped off, and a photoresist mask 120 having a via pattern is applied on the top hard mask 104 and the exposed embedded hard mask 114. A via 122 is formed in the stack 100 by etching the via mask 120 through the etch stop layer 114 and interlayer dielectric 112, stopping on the diffusion barrier 108.
In FIG. 1D, the exposed diffusion barrier 108 has been opened up via an etch process, and the via mask (120 in FIG. 1C) has been stripped off. Copper 124 is deposited into the trench 118 and the via 122 and polished back to the surface of the trench 118. The trench 118 and via 122 are typically lined with a material such as tantalum to prevent copper from diffusing into the interlayer dielectrics 110, 112. In FIG. 1E, a blanket of diffusion barrier 125 is deposited on the stack 100 to cap the copper 124.
FIGS. 1F-1I illustrate a via-first dual-damascene process. In FIG. 1F, a photoresist mask 126 having a via pattern is applied on the top hard mask 104. A via 128 is formed in the stack 100 by etching the via mask 126 through the top hard mask 104, the interlayer dielectric 110, the embedded hard mask 114, and the interlayer dielectric 112, stopping on the diffusion barrier 108. In FIG. 1G, the photoresist mask (126 in FIG. 1F) has been stripped off, and a photoresist mask 130 having a trench pattern is applied on the top hard mask 104. A trench 132 is formed in the stack 100 by etching the trench mask 130 through the top hard mask 104 and the interlayer dielectric 110, stopping on the embedded hard mask 114.
In FIG. 1H, the exposed bottom hard mask 114 has been opened up via an etch process, and the trench mask (130 in FIG. 1G) has been stripped off. Copper 134 is deposited into the via 128 and trench 132 and polished back to the surface of trench 132. The via 128 and trench 132 are typically lined with a material such as tantalum to prevent copper from diffusing into the interlayer dielectrics 110, 112. In FIG. 1I, a blanket of diffusion barrier 135 is deposited on the stack 100 to cap the copper 134.
In a trench etch, for example, the embedded hard mask 114 typically remains in the dielectric film stack 106r. When used as an etch stop layer, the embedded hard mask 114 is required to have selectivity to etching, which typically means that the embedded hard mask 114 has a significantly slower etch rate compared to the interlayer dielectric 110. Commonly, materials used as etch stop layers, such as SiNx or SiC, tend to have a high permittivity (κ) value relative to the low-κ interlayer dielectrics, which raises the overall κ value of the dielectric film stack 106. An increase in the overall κ value of the dielectric film stack 106 results in an increase in parasitic capacitance and compromises the ability of the stack to mitigate electrical delays. Thus, it is desirable to eliminate the high-κ embedded hard mask 114 or, at least, reduce its contribution to parasitic capacitance. However, control of etching is difficult when there is no effective etch stop layer.
One method for controlling etching when there is no effective etch stop layer is timed-etch. However, timed-etch may have a very low yield because it does not account for incoming material variations, e.g., variations in film thicknesses from one stack to the next, differences in etch rates as a result of material composition, and differences in etch rates of substantially identical etch systems.
Single or multiple discrete wavelength interferometry is an example of an optical diagnostic method that does not require an etch stop layer to detect an endpoint in an etching process. In single-wavelength interferometry, a light beam is directed on the surface of the wafer. The reflected signals from the wafer then combine constructively or destructively to produce a periodic interference fringe. When a predetermined number of fringes corresponding to the thickness of material to be removed has been counted, the etching process is stopped. In general, strong reflections from the interfaces (or underlying metal features) in a dual damascene structure make it difficult to use the interferometric approach for detecting an etching endpoint. Further, the interferometric approach has limited capability to account for incoming material variations because it measures relative changes in feature dimensions as opposed to absolute feature dimensions.
From the foregoing, there is desired a method for detecting an endpoint during etching of a film stack without significantly increasing the overall κ value of the film stack.